Some general information regarding RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) processors and the difference between RISC and CISC microprocessors are discussed here.
In the early ’50s and 60’s IBM 360, the mainframe machine used simple fixed-length instructions. The IMB 360’s instruction set was a classic CISC design, but the microcode engine that actually executed the instruction set was a simple RISC processor.
So RISC concepts are not new, they were just waiting for the cost of technology to justify the RISC approach.
RISC got a significant boost as the result of software work being done at IBM. As a result of IBM’s work on compiler technology, it was recovered that most of the complex instructions in the CISC design were rarely used.
By inspecting the compiler-generated machine language output, it is found that often as little of 10% of the CISC machine language instruction set accounted for over 90% of the code generated by the compiler.
IBM and several universities began to do research into the development of simple computer designs that had very few instructions, large register arrays simple load-and-store access to main memory, and with instructions executed in one clock cycle. As a result, RISC processors arrived.
RISC processors were extensively used in high-performance workstations for scientific and engineering applications. As the RISC processors evolved, their true advantage began to emerge.
Difference between RISC and CISC microprocessors
Reduced Instruction Set Computer
Complex Instruction Set Computer.
|The microprocessor is designed using hardwired control.||The microprocessor is designed using code control|
|It executes at least one instruction in a cycle||Several cycles may be required to execute one instruction|
|The instructions have simply fixed formats with few addressing modes.||The instructions have variable formats with several complex addressing modes.|
|It has several general-purpose resisters and large cache memory.||It has a small number of general-purpose registers|
|The instruction set of RISC microprocessors typically includes the only register to register load and store.||The instruction set of CISC microprocessor includes several instructions to access memory and CPU registers.|
|Pipelining and superscalar architectures are the base methods to design a RISC processor||Pipelining and superscalar features are not the bases to design such processors, although, many CISC microprocessors use several features if RISCs such as: pipelining, to increase its performance.|
In the final analysis, RISC designs appear superior. Similar internal clock speeds, RISC processors consistently outperform CISC processors.
Since RISC processors do not require a lot of silicon, it adds superscalar execution units, more powerful floating-point units, and large on-chip caches. Or more simply RISC designs take less space and allow more functions on a chip than CISC design.
RISC ideas have infiltrated to every high-performance design. Intel, the main designer of CISC microprocessors, also uses basic RISC features to improve the performance of the processor. For Example:
- Intel 80486 uses features like scalar, pipeline
- Intel Pentium uses features like superscalar and super pipeline.
The upcoming new Pentium PC Processors also contain more or less many characteristics of RISC processors to increase their speed and performance. So all the next generation CISCs will evolve with the features of RISC processors.
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